VG.rtl

SYSTEM READY // VARADA GOVIND AAKULA

🏆 VDAT 2026 • Accepted Paper

DIGITAL LOGIC,
REAL SILICON.

Hardware Researcher at IIIT Allahabad specializing in RTL Design, SystemVerilog, RISC-V Microarchitecture, Hardware Verification, FPGA Acceleration, and CMOS VLSI. Passionate about building high-performance digital systems from architecture to silicon.

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PROJECTS

10+

PUBLICATION

VDAT 2026

OPEN SOURCE

GitHub

FOCUS

PPA-aware

01 // PROJECTS

Selected Work

PYTHON / MULTI-AGENT AI / EDA

Argus: AI Hardware Debugger WIP

A multi-agent AI framework for hardware debugging that combines deterministic RTL analysis, simulation-log parsing, waveform intelligence, and protocol checking with LLM-based reasoning. Decomposes debugging into specialized AI agents while an orchestration layer coordinates evidence collection to generate explainable root-cause reports and recommend potential RTL fixes.

RESEARCH FRAMEWORK

VERILOG / EDGE AI

Task-Aware Object Detection

Built a heterogeneous inference pipeline. Engineered a 16x16 INT8 systolic array delivering 51.2 GOPS at 200 MHz. Reduced memory bandwidth 256x via sparse BRAM addressing and hid latency via Ping-Pong AXI4 SG-DMA.

DVCON 2026 CONTEST

OPEN REPOSITORY

SYSVERILOG / RISC-V / RTL

Prolepsis: ISA-Agnostic Predictive TMU

Architected an ISA-agnostic RTL Thermal Management Unit (TMU) for multicore RISC-V processors. Designed a Kalman predictor and policy FSM for proactive thermal management without ISA modifications. Achieved 96.3% execution under an 85°C thermal limit (vs 68.7% baseline) using 18,015 LUTs on Xilinx UltraScale+.

ACCEPTED FOR PRESENTATION • VDAT 2026

OPEN REPOSITORY

CRYPTO / AXI4

GridLock AES: 1.6 Gbps

SystemVerilog hardware accelerator achieving 1.66 Gbps and 150 MHz timing closure (WNS: +1.049 ns). Reduced logic area by 40% via Composite Field Arithmetic for a BRAM-less S-Box (2,581 LUTs, 539 Registers).

OPEN REPOSITORY
VERILOG / RISC-V

RV32I Soft-Core

Single-cycle RISC-V core meeting 100 MHz timing on Nexys 4 DDR. Achieved ultra-low footprint (300 LUTs) and minimized on-chip power to 1.89 W. Includes custom MMIO.

OPEN REPOSITORY
VLSI / SPICE

CMOS Cell Library

Standard cell library (Inverter, NAND, FF) and hierarchical 1-Bit Adder designed using NMOS/PMOS models. Validated via rigorous transient and DC sweep analysis.

OPEN REPOSITORY

Hardware Protocol Stack

UART Controller

Configurable baud-rate 16-bit transceiver.
SPI Core

Master/Slave architecture for high-speed sync.
I2C Controller

Multi-master capable with robust CDC handling.
02 // TIMELINE

Career & Education

JAN 2026 - JUL 2026

Research Intern

Indian Institute of Information Technology, Allahabad

Architecting Prolepsis (an RTL Thermal Management Unit) for a 4-core RISC-V cluster. Designed a Kalman predictor and policy FSM for proactive throttling and task migrations to bypass firmware delays.

AUG 2024 - PRESENT

IoT Wing Coordinator

Tesla Electronics Society, IIIT Allahabad

Leading practical hardware initiatives, lab planning, and mentoring 20+ members on digital design fundamentals and Verilog coding standards.

2023 - 2027 (EXPECTED)

B.Tech Electronics & Communication

Indian Institute of Information Technology, Allahabad

Core coursework focusing on Digital Logic Design, CMOS VLSI Design, Low Power Design, Computer Architecture, Signals & Systems, and Computer Networks.

03 // PUBLICATIONS

Research Publications

🏆 ACCEPTED @ VDAT 2026
Accepted Conference Paper RTL Research

Prolepsis:
ISA-Agnostic RTL Predictive Thermal
Management for Multicore Processors

Designed an ISA-agnostic RTL Thermal Management Unit (TMU) that proactively predicts thermal hotspots using a Kalman predictor and policy FSM, enabling runtime thermal management without ISA modifications while maintaining 96.3% execution under an 85°C thermal limit.

SystemVerilog

RTL

RISC-V

FPGA

Kalman Filter

Thermal Management

04 // ARSENAL

Technical Proficiency

RTL Design

  • SystemVerilog & UVM
  • Verilog & VHDL
  • RISC-V microarchitecture
  • AXI4 Integration
  • CDC & Data Synchronization

Firmware & Software

  • C and C++
  • Python scripting
  • Assembly-level Programming
  • Linux Environments

Tools

  • Xilinx Vivado
  • LTspice
  • GTKWave
  • ModelSim
  • MATLAB & Git/GitHub

Concepts

  • Digital Logic & FSM Design
  • Static Timing Analysis (STA)
  • CMOS VLSI
  • FPGA Implementation Flow

05 // CONTACT

Let's Build Hardware That Matters Let's Build Hardware That Matters

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Copyright 2026 Varada Govind Aakula